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| K524G2GACB-A050 MCP MEMORY MCP Specification 4Gb NAND Flash + 2Gb Mobile DDR INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Revision 1.3 November 2009 K524G2GACB-A050 Document Title Multi-Chip Package MEMORY 4Gb (256M x16) NAND Flash Memory / 2Gb (64M x32) Mobile DDR SDRAM MCP MEMORY 1. Revision History Revision No. 0.0 History Initial issue. - 4Gb NAND Flash W-die_ Ver 0.0 - 2Gb M-DDR SDRAM B-die_Ver 1.0 Draft Date May. 8, 2009 Remark Preliminary 1.0 Aug. 17, 2009 Final 1.1 Sep. 03, 2009 Final 1.2 Oct. 8, 2009 Final 1.3 Nov. 26, 2009 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. -2- Revision 1.3 November 2009 K524G2GACB-A050 Multi-Chip Package MEMORY 4Gb (256M x16) NAND Flash Memory / 2Gb (64M x32) Mobile DDR SDRAM MCP MEMORY 2. FEATURES Operating Frequency DDR333 Speed @CL31) 166MHz DDR400 200MHz Note: 1) CAS Latency Address configuration Organization 64Mx32 Bank BA0,BA1 Row A0 - A13 Column A0 - A9 - DM is internally loaded to match DQ and DQS identically. SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -3- Revision 1.3 November 2009 K524G2GACB-A050 3. GENERAL DESCRIPTION MCP MEMORY The K524G2GACB is a Multi Chip Package Memory which combines 4Gbit NAND Flash Memory an 2Gbit DDR synchronous high data rate Dynamic RAM. NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250s on the (1K+32)Word page and an erase operation can be performed in typical 2ms on a (64K+2K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the devices extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. In 2Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The K524G2GACB is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type. -4- Revision 1.3 November 2009 K524G2GACB-A050 4. Pin CONFIGURATION MCP MEMORY - 1 2 3 4 5 6 7 8 9 10 A - DNU - - - - - - DNU DNU B NC NC /REn CLEn VCCn /CEn /WEn VDDd VSSd NC C VSSd A4d /WPn ALEn VSSn R/Bn DQ31d DQ30d VDDQd VSSQd D VDDd A5d A7d A9d DQ25d DQ27d DQ29d DQ28d VSSQd VDDQd E A6d A8d CKEd DQ18d DQS3d DQ22d DM3d DQ26d VDDQd VSSQd F A12d A11d NC DQ17d DQ19d DQ24d DQ23d DM2d VSSQd VDDQd G NC /RASd DQ15d DQ16d DQS1d DM1d DQ9d CKd VDDQd VSSQd H VDDd /CASd DQ20d DQ21d DQ13d DQ12d DQS2d /CKd VSSd VDDd J VSSd /CSd BA0d DQ14d DQ11d DQ10d DQS0d DM0d VSSQd VDDQd K /WEd BA1d A10d A0d DQ7d DQ8d DQ6d DQ4d VDDQd VSSQd L A1d A2d A3d DQ0d DQ1d DQ2d DQ3d DQ5d VDDQd VSSQd M VDDd VSSd A13d NC IO3n IO5n IO14n IO7n VSSQd VDDQd N IO0n IO1n IO2n IO10n VCCn IO6n IO13n IO15n VDDQd VSSQd P NC IO8n IO9n IO11n IO12n VSSn IO4n VDDd VSSd NC R DNU DNU - - - - - - DNU DNU 137 FBGA: Top View (Ball Down) NAND M-DDR Power Ground NC/DNU -5- Revision 1.3 November 2009 K524G2GACB-A050 5. PIN DESCRIPTION Pin Name CKd,/CKd CKEd /CSd /RASd /CASd /WEd A0d ~ A13d BA0d ~ BA1d DM0d ~ DM3d DQS0d~DQS3d DQ0d ~ DQ31d VDDd VDDQd VSSd VSSQd Pin Function(M-DDR) System Clock & Differential Clock Clock Enable Chip Selection Row Address Strobe Column Address Strobe Write Enable Address Input Bank Address Input Input Data Mask Data Input / Output Data Input / Output Power Supply Data Out Power Ground DQ Ground Pin Name NC DNU No Connection Do Not Use Pin Name /CEn /REn /WPn /WEn ALEn CLEn R/Bn IO0n ~ IO15n VCCn VSSn MCP MEMORY Pin Function(NAND Flash) Chip Enable Read Enable Write Protection Write Enable Address Latch Enable Command Latch Enable Ready/Busy Output Data Input/Output Power Supply Ground Pin Function -6- Revision 1.3 November 2009 K524G2GACB-A050 6. ORDERING INFORMATION MCP MEMORY K5 2 4G 2G A C B - A 0 50 Samsung MCP Memory(2chips) Device Type NAND Flash + Mobile DDR NAND Flash Density, Organization 4G : 4Gbit, x16 Mobile DDR Density, Organization 2G : 2Gbit, x32 Operating Voltage A: 1.8V / 1.8V M-DDR Speed 50 : 400Mbps@CL3 NAND Flash Speed 0 : None Package A : FBGA(HF, LF) Version B : 3rd Generation Flash Block Architecture C : Uniform Block -7- Revision 1.3 November 2009 K524G2GACB-A050 7. FUNCTIONAL BLOCK DIAGRAM VCCn VSSn MCP MEMORY /CEn /REn /WPn /WEn ALEn CLEn R/Bn 4Gb NAND Flash Memory IO0n to IO15n VDDd VDDQd VSSd VSSQd CKd,/CKd CKEd /CSd /RASd /CASd /WEd A0d ~ A13d BA0d ~ BA1d DM0d ~ DM3d DQS0d ~ DQS3d 2Gb Mobile DDR DQ0d~DQ31d -8- Revision 1.3 November 2009 K524G2GACB-A050 8. PACKAGE DIMENSION 137-Ball Fine pitch Ball Grid Array Package (measured in millimeters) MCP MEMORY Units:millimeters #A1 INDEX MARK 10.500.10 0.10 MAX (Datum A) A B C D (Datum B) E F G H J K L M N P R 5.60 0.320.05 1.100.10 TOP VIEW 137-0.450.05 0.20 M A B 10.500.10 0.80 x 9 = 7.20 10 9 8 7 6 5 4 3 2 1 A B #A1 0.80 3.60 0.80 BOTTOM VIEW -9- Revision 1.3 November 2009 0.80 x 14 = 11.20 13.000.10 13.000.10 K524G2GACB-A050 MCP MEMORY 4Gb (256M x16) NAND Flash W-die - 10 - Revision 1.3 November 2009 K524G2GACB-A050 Figure 1. Functional Block Diagram(x8) VCC VSS A12 - A30* X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4,096M + 128M Bit for 4Gb 8,192M + 256M Bit for 8Gb DDP NAND Flash ARRAY MCP MEMORY A0 - A11 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0 CE RE WE Control Logic & High Voltage Generator Global Buffers I/0 7 CLE ALE WP Figure 2. Array Organization(x8) 1 Block = 64 Pages (128K + 4K) Byte 4,096 blocks for 4Gb 8,192 blocks for 8Gb DDP 2K Bytes 64 Bytes 1 Page = (2K + 64)Bytes 1 Block = (2K + 64)Byte x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 4,096 Blocks = 4,224 Mbits for 4Gb 8 bit 1 Device = (2K+64)B x 64Pages x 8,192 Blocks = 8,448 Mbits for 8Gb DDP Page Register 2K Bytes 64 Bytes I/O 0 ~ I/O 7 Table 1. Array address : (x8) I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A30 is Row address for 8G DDP. In case of 4G Mono, A30 must be set to "Low" I/O 1 A1 A9 A13 A21 A29 I/O 2 A2 A10 A14 A22 *A30 I/O 3 A3 A11 A15 A23 *L I/O 4 A4 *L A16 A24 *L I/O 5 A5 *L A17 A25 *L I/O 6 A6 *L A18 A26 *L I/O 7 A7 *L A19 A27 *L Address Column Address Column Address Row Address Row Address Row Address A0 A8 A12 A20 A28 - 11 - Revision 1.3 November 2009 K524G2GACB-A050 Figure 3. Functional Block Diagram(x16) VCC VSS A11 - A29* X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4,096M + 128M Bit for 4Gb 8,192M + 256M Bit for 8Gb DDP NAND Flash ARRAY MCP MEMORY A0 - A10 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0 CE RE WE Control Logic & High Voltage Generator Global Buffers I/0 15 CLE ALE WP Figure 4. Figure 2-2. Array Organization(x16) 1 Block = 64 Pages (64K + 2K)Word 4,096 blocks for 4Gb 8,192 blocks for 8Gb DDP 1K Words 32 Words 1 Page = (1K + 32)Word 1 Block = (1K + 32)Word x 64 Pages = (64K + 2K)Words 1 Device = (1K + 32)Word x 64Pages x 4,096 Blocks = 4,224 Mbits for 4Gb 1 Device = (1K + 32)Word x 64Pages x 8,192 Blocks 16 bit = 8,448 Mbits for 8Gb DDP Page Register 1K Words 32 Words I/O 0 ~ I/O 15 Table 2. Array address : (x16) I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A29 is Row address for 8G DDP. In case of 4G Mono, A29 must be set to "Low" I/O 1 A1 A9 A12 A20 A28 I/O 2 A2 A10 A13 A21 *A29 I/O 3 A3 *L A14 A22 *L I/O 4 A4 *L A15 A23 *L I/O 5 A5 *L A16 A24 *L I/O 6 A6 *L A17 A25 *L I/O 7 A7 *L A18 A26 *L I/O 8~I/O 15 *L *L *L *L *L Address Column Address Column Address Row Address Row Address Row Address A0 A8 A11 A19 A27 - 12 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 1.0 Product Introduction NAND Flash Memory has addresses multiplexed into 8 I/Os(x16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 3 defines the specific commands of the KF94GxxQ2W/KF88GxxQ2W. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. Table 3. Command Sets Function Read Read ID Read for Copy Back Reset Page Program Copy-Back Program Block Erase Random Data Input(1) Random Data Output(1) Read Status NOTE : 1) Random Data Input/Output can be executed in a page. Caution : Any undefined command inputs are prohibited except for above command set of Table 3. 1st Cycle 00h 90h 00h FFh 80h 85h 60h 85h 05h 70h 2nd Cycle 30h 35h 10h 10h D0h E0h - Acceptable Command during Busy O O - 13 - Revision 1.3 November 2009 K524G2GACB-A050 1.1 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Current Symbol VCC VIN VI/O TBIAS TSTG IOS MCP MEMORY Rating -0.6 to + 2.45 -0.6 to + 2.45 -0.6 to Vcc + 0.3 (< 2.45V) -30 to +125 -65 to +150 5 Unit V C C mA NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1.2 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA=-25 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 1.7 0 Typ. 1.8 0 Max 1.95 0 Unit V V 1.3 DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) Parameter Operating Current Page Read with Serial Access Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH (1) Test Conditions tRC=42ns CE=VIL, IOUT=0mA 4Gb,CE=VIH, WP=0V/VCC 8Gb DDP,CE=VIH, WP=0V/VCC 4Gb,CE=VCC-0.2, WP=0V/VCC 8Gb DDP, CE=VCC-0.2, WP=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) IOH=-100A IOL=100uA VOL=0.1V Min 0.8xVCC -0.3 Vcc-0.1 3 Typ Max Unit 15 25 mA 10 20 4 1 2 50 100 10 10 VCC+0.3 0.2xVcc 0.1 mA V A VIL(1) VOH VOL IOL(R/B) NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc=1.8V, TA=25C. Not 100% tested. - 14 - Revision 1.3 November 2009 K524G2GACB-A050 1.4 VALID BLOCK Parameter 4Gb 8Gb DDP Symbol NVB NVB Min 4,016 8.032 Typ. Max 4,096 8,192 MCP MEMORY Unit Blocks Blocks NOTE : 1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8 : 1bit/ 512Byte, x16 : 1bit/ 256Word ECC. 3) Each mono chip in th KF88GxxQ2W has maximum 40 invalid blocks. 1.5 AC TEST CONDITION (TA=-25 to 85C, Vcc=1.7V~1.95V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=30pF 1.6 CAPACITANCE(TA=25C, VCC=1.8V, f=1.0MHz) Item Input/Output Capacitance (Mono) Input Capacitance (Mono) Input/Output Capacitance (DDP) Input Capacitance (DDP) Symbol CI/O CIN CI/O CIN Test Condition VIL=0V VIN=0V VIL=0V VIN=0V Min Max 10 10 20 20 Unit pF pF pF pF NOTE : Capacitance is periodically sampled and not 100% tested. 1.7 MODE SELECTION CLE H L H L L L X X X X X ALE L H L H L L X X X X (1) CE L L L L L L X X X X H WE RE H H H H H WP X X H H H X X H H L 0V/VCC (2) Mode Read Mode Write Mode Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Command Input Address Input(5clock) Command Input Address Input(5clock) H X X X X X H X X X X X NOTE : 1) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby. - 15 - Revision 1.3 November 2009 K524G2GACB-A050 1.8 Read / Program / Erase Characteristics Parameter Program Time Number of Partial Program Cycles Block Erase Time Symbol tPROG Nop tBERS Min Typ 250 2 MCP MEMORY Max 750 4 10 Unit s cycles ms NOTE : 1) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25C temperature. 1.9 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Address to Data Loading Time Symbol tCLS(1) tCLH tCS(1) tCH tWP tALS(1) tALH tDS (1) Min 21 5 21 5 21 21 5 20 5 40 10 100 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns tDH tWC tWH tADL (2) NOTE : 1) The transition of the corresponding control pins must occur only once while WE is held low 2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle - 16 - Revision 1.3 November 2009 K524G2GACB-A050 1.10 AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy WP Low to WE Low (disable mode) WP High to WE Low (enable mode) Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don't Care RE High to Output Hold CE High to Output Hold RE High Hold Time Output Hi-Z to RE Low RE High to WE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tWW tRC tREA tCEA tRHZ tCHZ tCSD tROH tCOH tREH tIR tRHW tWHR tRST Min 10 10 20 21 100 42 0 15 15 10 0 100 60 Max 40 100 30 35 100 30 5/10/500(1) MCP MEMORY Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s NOTE : 1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s. - 17 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 2.0 NAND Flash Technical Notes 2.1 Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with x8:1bit/ 512Byte, x16:1bit/256Word ECC. 2.2 Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte(1st word) in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048(x16:1024). Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 5). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address * No Check "FFh(x16:FFFFh)" at the column address 2048(x16:1024) of the 1st and 2nd page in the block Create (or update) Initial Invalid Block(s) Table Check "FFh(x16:FFFFh)" Yes No Last Block ? Yes End Figure 5. Flow chart to create initial invalid block table - 18 - Revision 1.3 November 2009 K524G2GACB-A050 NAND Flash Technical Notes (Continued) MCP MEMORY 2.3 Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement should be done upon erase or program error. Failure Mode Write Read Erase Failure Program Failure Up to 1 Bit-Failure Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verity ECC -> ECC Correction ECC : Error Correcting Code --> Hamming code Example) 1bit correction & 512-byte Note) A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Software scheme such as caching into RAM is recommended. Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Program Completed No Program Error * * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. - 19 - Revision 1.3 November 2009 K524G2GACB-A050 NAND Flash Technical Notes (Continued) Erase Flow Chart MCP MEMORY Read Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed No No Erase Error * Reclaim the Error Verify ECC Yes Page Read Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st (n-1)th nth (page) { { Block A 1 an error occurs. Buffer memory of the controller. Block B 2 1st (n-1)th nth (page) * Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme. - 20 - Revision 1.3 November 2009 K524G2GACB-A050 NAND Flash Technical Notes (Continued) MCP MEMORY 2.4 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. Page 63 (64) : Page 63 (64) : Page 31 (32) : Page 31 (1) : Page 2 Page 1 Page 0 (3) (2) (1) Page 2 Page 1 Page 0 (3) (32) (2) Data register From the LSB page to MSB page DATA IN: Data (1) Data (64) Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) - 21 - Revision 1.3 November 2009 K524G2GACB-A050 2.5 System Interface Using CE don't-care. MCP MEMORY For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte(1,056Word) data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. Figure 6. Program Operation with CE don't-care. CE don't-care I/Ox 80h Address(5Cycles) Data Input Data Input ALE WE CE CLE 10h tCS CE tCH CE tCEA tREA tWP WE I/Ox out RE Figure 7. Read Operation with CE don't-care. CE don't-care CE RE ALE R/B tR I/Ox WE 00h Address(5Cycle) 30h Data Output(serial access) - 22 - Revision 1.3 November 2009 CLE K524G2GACB-A050 NOTE : Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) I/O I/Ox I/O 0 ~ I/O 7 I/O 0 ~ I/O 7 I/O 0 ~ I/O 15 I/O 0 ~ I/O 15 DATA Data In/Out ~2,112byte ~2,112byte ~1,056Word ~1,056Word Col. Add1 A0~A7 A0~A7 A0~A7 A0~A7 Col. Add2 A8~A11 A8~A11 A8~A10 A8~A10 ADDRESS Row Add1 A12~A19 A12~A19 A11~A18 A11~A18 MCP MEMORY Row Add2 A20~A27 A20~A27 A19~A26 A19~A26 Row Add3 A28~A29 A28~A30 A27~A28 A27~A29 - 23 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 3.0 TIMING DIAGRAMS 3.1 Command Latch Cycle CLE tCLS tCS CE tCLH tCH tWP WE tALS ALE tDS I/Ox tALH tDH Command - 24 - Revision 1.3 November 2009 K524G2GACB-A050 3.2 Address Latch Cycle tCLS CLE tCS tWC CE tWC tWC tWC MCP MEMORY tWP WE tALS ALE tDS I/Ox tDH tWH tALH tWP tALS tALH tWH tWP tALS tWH tALH tWP tALS tWH tALH tALS tALH tDS tDH tDS tDH tDS tDH tDS tDH Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 3.3 Input Data Latch Cycle tCLH CLE tCH CE tWC ALE tALS WE tDS I/Ox tWH tDH tDS tDH tWP tWP tWP tDH tDS DIN 0 DIN 1 DIN final - 25 - Revision 1.3 November 2009 K524G2GACB-A050 3.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) CE tREA RE tRHZ I/Ox tRR R/B Dout Dout tRHZ tROH Dout tRC tRP tREH MCP MEMORY tCHZ tREA tCOH NOTE : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 3.5 Status Read Cycle tCLR CLE tCLS tCS CE tCH tCEA tWHR RE tDS I/Ox 70h tDH tIR tREA tRHZ tRHOH tCLH tWP WE tREA tCHZ tCOH Status Output - 26 - Revision 1.3 November 2009 K524G2GACB-A050 3.6 Read Operation tCLR CLE MCP MEMORY CE tWC WE tWB tAR ALE tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tRC tRHZ 30h tCOH Dout N Dout N+1 Dout M Column Address Row Address Busy R/B 3.7 Read Operation(Intercepted by CE) tCLR CLE CE tCSD WE tWB tAR ALE tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h tCHZ tRC Dout N Dout N+1 Dout N+2 Column Address Row Address R/B Busy - 27 - Revision 1.3 November 2009 K524G2GACB-A050 CLE tCLR 3.8 Random Data Output In a Page CE WE tWB tAR tRHW tWHR - 28 - ALE tR tRC tREA RE tRR Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 I/Ox Column Address Row Address 00h 30h Dout N Dout N+1 05h Col Add1 Col Add2 E0h Dout M Dout M+1 Column Address Busy R/B MCP MEMORY Revision 1.3 November 2009 K524G2GACB-A050 3.9 Page Program Operation CLE MCP MEMORY CE WE tADL ALE tWB tPROG tWHR RE Din Din N M 1 up to m Byte Serial Input I/Ox 80h tWC tWC tWC Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 10h Program Command 70h Read Status Command I/O0 SerialData Column Address Input Command Row Address R/B I/O0=0 Successful Program I/O0=1 Error in Program NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. - 29 - Revision 1.3 November 2009 CLE CE K524G2GACB-A050 WE tWC tWC tADL tWB tPROG tADL tWC ALE tWHR RE Serial Data Column Address Input Command Row Address Serial Input Serial Input Random Data Column Address Input Command I/Ox 80h Col. Add2 Row Add1 Row Add2 Row Add3 Col. Add1 Din N Din M 85h Col. Add1 Col. Add2 Din J Din K 10h Program Command 70h Read Status Command I/O0 3.10 Page Program Operation with Random Data Input NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 2) After serial input of data for random data input, status read(70h) command can be issued for reading status, and only status bit(I/O 6) is valid. R/B - 30 - MCP MEMORY Revision 1.3 November 2009 K524G2GACB-A050 CLE CE tWHR tPROG tWB tRC tADL tWC tWB WE ALE tR 3.11 Copy-Back Program Operation with Random Data Input Busy Copy-Back Data NOTE : Input Command 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. - 31 35h Data N Data 1 RE I/Ox 85h Row Address 00h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Data 1 Data N 10h Column Address Row Address 70h I/Ox Read Status Command Column Address R/B Busy I/O0=0 Successful Program I/O0=1 Error in Program MCP MEMORY Revision 1.3 November 2009 K524G2GACB-A050 3.12 Block Erase Operation CLE MCP MEMORY CE tWC WE tWB ALE tBERS tWHR RE I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0 Row Address Auto Block Erase Setup Command Erase Command R/B Busy Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase - 32 - Revision 1.3 November 2009 K524G2GACB-A050 3.13 Read ID Operation CLE MCP MEMORY CE WE tAR ALE RE tREA I/Ox 90h Read ID Command 00h Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Maker Code Device Code Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) Device Code (2nd Cycle) ACh A3h BCh B3h 3rd Cycle 00h 01h 00h 01h 4th Cycle 15h 15h 55h 55h 5th Cycle 56h 5Ah 56h 5Ah 3.13.1 ID Definition Table 90 ID : Access command = 90H Description 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte st Maker Code Device Code Internal Chip Number Page Size, Block Size,Redundant Area Size, Organization Plane Number, Plane Size, ECC Level - 33 - Revision 1.3 November 2009 K524G2GACB-A050 3rd ID Data ITEM Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not supported supported Not supported supported 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 I/O # 7 6 5 4 3 MCP MEMORY 2 1 0 0 1 1 0 0 1 0 1 Internal Chip Number Cell Type 0 1 0 1 Number of Simultaneously Programmed Pages Interleave Program Between Multii-Chips Cache Program 4th ID Data ITEM Description 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 Reserved Reserved X8 X16 0 or 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O # 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 Page Size (without Redundant Area) Block Size (without Redundant Area) Redundant Area Size (Byte/512byte) Organization Reserved - 34 - Revision 1.3 November 2009 K524G2GACB-A050 5th ID Data ITEM Description 1bit ECC/512Byte 2bit ECC/512Byte 4bit ECC/512Byte Reserved 1 2 4 8 64KB 128KB 256KB 512KB 1Gb 2Gb 4Gb 8Gb Reserved 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 I/O # 7 6 5 4 3 MCP MEMORY 2 1 0 0 1 1 0 0 1 0 1 ECC level Plane Number 0 1 0 1 Plane Size (without Redundant Area) Reseved - 35 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 4.0 Device Operation 4.1 PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes(1,056 Wrods) of data within the selected page are transferred to the data registers in 40s(tR) typically. The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 42ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Figure 8. Read Operation ALE R/B RE I/Ox 00h WE CE CLE tR Address(5Cycle) Col. Add.1,2 & Row Add.1,2,3 30h Data Output(Serial Access) Data Field Spare Field - 36 - Revision 1.3 November 2009 K524G2GACB-A050 4.2 PAGE PROGRAM MCP MEMORY The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or consecutive byte up to 2,112 bytes(1,056 Wrods), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112 bytes(1,056 Wrods) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The bytes(words) other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 9). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 9. Program & Read Status Operation R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add.1,2,3 Data Fail tPROG "0" 10h 70h I/O0 "1" Pass Figure 10. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data Address & Data Input Col. Add.1,2 Data tPROG "0" 85h 10h 70h I/O0 "1" Fail Pass - 37 - Revision 1.3 November 2009 K524G2GACB-A050 4.3 COPY-BACK PROGRAM MCP MEMORY Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112 bytes(1,056 Wrods) data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11 & Figure 12). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 12. Figure 11. Page Copy-Back Program Operation tR R/B I/Ox 00h Add.(5Cycles) 35h tPROG Data Output 85h Add.(5Cycles) 10h 70h I/O0 "1" Fail "0" Pass Col. Add.1,2 & Row Add.1,2,3 Source Address Col. Add.1,2 & Row Add.1,2,3 Destination Address NOTE : 1) Copy-Back Program operation is allowed only within the same memory plane. Figure 12. Page Copy-Back Program Operation with Random Data Input tPROG R/B I/Ox 00h Add.(5Cycles) 35h tR Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Col. Add.1,2 Data 10h 70h Col. Add.1,2 & Row Add.1,2,3 Source Address Col. Add.1,2 & Row Add.1,2,3 Destination Address There is no limitation for the number of repetition. 4.4 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only Block address is valid while page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence. - 38 - Revision 1.3 November 2009 K524G2GACB-A050 Figure 13. Block Erase Operation tBERS MCP MEMORY R/B I/Ox 60h "0" Address Input(3Cycle) Row Add 1,2,3 Fail D0h 70h I/O0 "1" Pass 4.5 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. Table 4. Status Register Definition for 70h Command I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not Use Not use Not use Not use Not Use Not Use Ready/Busy Write Protect Pass : "0" Don't -cared Don't -cared Don't -cared Don't -cared Don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition Fail : "1" NOTE : 1) I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. - 39 - Revision 1.3 November 2009 K524G2GACB-A050 4.6 Read ID MCP MEMORY The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence. Figure 14. Read ID Operation CLE CE WE tAR ALE tWHR RE I/OX 90h 00h Address. 1cycle tCLR tCEA tREA ECh Device Code Device code 3rd Cyc. 4th Cyc. 5th Cyc. Maker code Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) Device Code (2nd Cycle) ACh A3h BCh B3h 3rd Cycle 00h 01h 00h 01h 4th Cycle 15h 15h 55h 55h 5th Cycle 54h 58h 54h 58h 4.7 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/ B pin changes to low for tRST after the Reset command is written. Refer to Figure 15 below. Figure 15. RESET Operation R/B I/OX FFh tRST Table 5. Device Status After Power-up Operation mode Mode 00h Command is latched After Reset Waiting for next command - 40 - Revision 1.3 November 2009 K524G2GACB-A050 4.8 READY/BUSY MCP MEMORY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.17). Its value can be determined by the following guidance. Vcc Rp VCC ibusy Ready Vcc R/B open drain output 1.8V device - VOL : 0.1V, VOH : VCC-0.1V VOH CL tf GND Device VOL Busy tr Figure 16. Rp vs tr ,tf & Rp vs ibusy @ Vcc = 1.8V, Ta = 25C , CL = 30pF 200n tr,tf [s] 1.70 2m 120 Ibusy [A] Ibusy 100n 30 1.7 0.85 60 90 0.57 0.43 1.7 1m tr tf 1.7 1.7 1K 2K 3K Rp(ohm) 4K Rp value guidance Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.) IOL + IL = 1.85V 3mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 41 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 5.0 DATA PROTECTION & POWER UP SEQUENCE The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides additional software protection. Figure 17. AC Waveforms for Power Transition ~ 1.5V VCC High ~ 1.5V WP WE 5 ms max 1ms Operation Invalid Don't care Ready/Busy Don't care - 42 - Revision 1.3 November 2009 K524G2GACB-A050 5.1 WP AC TIMING GUIDE Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: MCP MEMORY Figure 18. Program Operation 1. Enable Mode WE I/O WP R/B tww(min.100ns) 80h 10h 80h 2. Disable Mode WE I/O WP R/B tww(min.100ns) 10h Figure 19. Erase Operation 1. Enable Mode WE I/O WP R/B tww(min.100ns) 60h D0h 60h 2. Disable Mode WE I/O WP R/B tww(min.100ns) D0h - 43 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 2Gb (64M x32) M-DDR SDRAM B-die - 44 - Revision 1.3 November 2009 K524G2GACB-A050 1. Functional Description Figure 1. State diagram POWER APPLIED POWER ON PARTIAL SELF REFRESH MCP MEMORY PRECHARGE ALL BANKS REFS SELF REFRESH REFSX EMRS MRS MRS IDLE ALL BANKS PRECHARGED REFA AUTO REFRESH CKEL CKEH ACT POWER DOWN POWER DOWN CKEH CKEL WRITE WRITEA READA READ READ ROW ACTIVE BURST STOP READ WRITEA WRITE WRITEA READA WRITEA PRE PRE PRE READA READA PRE PRECHARGE PREALL Automatic Sequence Command Sequence - 45 - Revision 1.3 November 2009 K524G2GACB-A050 2. Mode Register Definition 2.1 Mode Register Set(MRS) MCP MEMORY The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on CS, RAS, CAS and WE(The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A13 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation. Figure 2. Mode Register Set BA1 BA0 A13 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 RFU1) 0 0 0 CAS Latency BT Burst Length Mode Register A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved Burst Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Reserved 2 4 8 16 Reserved Reserved Reserved NOTE : 1) RFU(Reserved for future use) should stay "0" during MRS cycle - 46 - Revision 1.3 November 2009 K524G2GACB-A050 Table 1. Burst address ordering for burst length Burst Length Starting Address (A3, A2, A1, A0) xxx0 xxx1 xx00 4 xx01 xx10 xx11 x000 x001 x010 8 x011 x100 x101 x110 x111 0000 0001 0010 0011 0100 0101 0110 16 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 MCP MEMORY Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 2 - 47 - Revision 1.3 November 2009 K524G2GACB-A050 2.2 Extended Mode Register Set(EMRS) MCP MEMORY The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A13 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A7 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. Figure 3. Extended Mode Register Set BA1 BA0 A13 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 1 0 RFU1) 0 0 DS RFU1) PASR Mode Register DS A7 0 0 0 0 1 1 1 1 A6 0 0 1 1 0 0 1 1 A5 0 1 0 1 0 1 0 1 Driver Strength Full 1/2 1/4 1/8 3/4 3/8 5/8 7/8 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 PASR Refreshed Area Full Array 1/2 Array 1/4 Array Reserved Reserved Reserved Reserved Reserved NOTE : 1) RFU(Reserved for future use) should stay "0" during EMRS cycle - 48 - Revision 1.3 November 2009 K524G2GACB-A050 2.3 Internal Temperature Compensated Self Refresh (TCSR) MCP MEMORY 1. In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refreshcycle automatically according to the real device temperature. 2. TCSR ranges for IDD6 shown in the table are as an example only. Max IDD6 valus for 45C, 85C are guaranteed. Typical values for 85 C, 70 C, 45 C and 15 C are obtained from device characterization. 3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Self Refresh Current (IDD6) Temperature Range Typ. 85 C 70 C 45 C 15 C 1100 750 450 300 900 Full Array Max 1800 Typ. 700 500 300 250 750 1/2 Array Max 1500 Typ. 500 350 250 200 650 1/4 Array Max 1300 uA Unit 2.4 Partial Array Self Refresh (PASR) 1. In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array. Figure 4. EMRS code and TCSR , PASR BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 - Full Array - 1/2 Array - 1/4 Array Partial Self Refresh Area - 49 - Revision 1.3 November 2009 K524G2GACB-A050 3. Absolute maximum ratings Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 2.7 -0.5 ~ 2.7 -0.5 ~ 2.7 -55 ~ +150 1.0 50 MCP MEMORY Unit V V V C W mA NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 4. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25C to 85C) Parameter Supply voltage(for device with a nominal VDD of 1.8V) I/O Supply voltage Input logic high voltage ( for Add.) Input logic high voltage (for Data) Input logic low voltage ( for Add.) Input logic low voltage (for Data) Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VIH(DC) Min 1.7 1.7 0.8 x VDDQ 0.7 x VDDQ -0.3 -0.3 0.9 x VDDQ -2 -5 Max 1.95 1.95 VDDQ+0.3 VDDQ+0.3 0.2 x VDDQ 0.3 x VDDQ 0.1 x VDDQ 2 5 Unit V V V V V V V V uA uA Note 1 1 2 VIL(DC) VOH(DC) VOL(DC) II IOZ 2 IOH = -0.1mA IOL = 0.1mA 3 NOTE : 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 3) Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. - 50 - Revision 1.3 November 2009 K524G2GACB-A050 5. DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85C) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol IDD0 IDD2P Test Condition tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE DDR 400 85 MCP MEMORY DDR 333 70 1.0 Unit Note mA IDD2PS all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE mA 1.0 8 mA 4 6 mA 5 15 mA 10 115 100 170 Values Typ 1100 750 450 300 700 500 300 250 500 350 250 200 650 1300 uA 750 1500 uA 900 Max 1800 uA 100 mA 80 170 1 IDD2N all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; Precharge Standby Curaddress and control inputs are SWITCHING; data bus inputs are STABLE rent all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; in non power-down mode IDD2NS address and control inputs are SWITCHING; data bus inputs are STABLE Active Standby Current in power-down mode IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE IDD3N one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; Active Standby Current address and control inputs are SWITCHING; data bus inputs are STABLE in non power-down mode (One Bank Active) IDD3NS one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Operating Current (Burst Mode) IDD4R IDD4W IDD5 one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer one bank active; BL = 4; tCK = tCKmin ; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer tRC tRFC; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE TCSR Range 85C Full Array CKE is LOW; t CK = t CKmin ; Extended Mode Register set to all 0's; address and control inputs are STABLE; data bus inputs are STABLE 70C 45C 15C 85C 1/2 Array 70C 45C 15C 85C 1/4 Array 70C 45C 15C NOTE : 1) IDD5 is measured in the below test condition. Density tRFC 128Mb 80 256Mb 80 512Mb 110 1Gb 140 2Gb 140 Unit ns Refresh Current mA Self Refresh Current IDD6 2) IDD specifications are tested after the device is properly intialized. 3) Input slew rate is 1V/ns. 4) Definitions for IDD: LOW is defined as V IN 0.1 * VDDQ ; HIGH is defined as V IN 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 5) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Samsung for more information. - 51 - Revision 1.3 November 2009 K524G2GACB-A050 6. AC Operating Conditions & Timming Specification Parameter/Condition Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VIX(AC) Min 0.8 x VDDQ -0.3 0.4 x VDDQ Max VDDQ+0.3 0.2 x VDDQ 0.6 x VDDQ MCP MEMORY Unit V V V Note 1 1 2 NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. - 52 - Revision 1.3 November 2009 K524G2GACB-A050 7. AC Timming Parameters & Specifications Parameter Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address delay Clock high level width Clock low level width DQ Output data access time from CK/CK DQS Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in low level width DQS falling edge to CK setup time DQS falling edge hold time from CK DQS-in cycle time Address and Control Input setup time fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate CL=3 CL=3 CL=3 CL=3 Symbol tCK tRC tRAS tRCD tRP tRRD tWR tDAL tCDLR tCCD tCH tCL tAC tDQSCK tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDQSH tDQSL tDSS tDSH tDSC tIS 1.1 0.9 tIH 1.1 tIPW tDS 0.58 0.48 tDH 0.58 tDIPW tLZ tHZ tWPST 0.4 1.2 1.0 5 0.6 0.4 0.7 1.2 1.0 0.7 0.6 2.2 0.48 1.3 2.2 0.6 1.3 1.1 0.9 0.4 0.75 0 0.25 0.4 0.4 0.2 0.2 0.9 0.9 1.1 0.6 0.6 DDR400 Min 5 55 40 20 15 10 12 2 1 0.45 0.45 2 2 0.55 0.55 5 5 0.4 1.1 0.6 1.25 0.9 0.4 0.75 0 0.25 0.4 0.4 0.2 0.2 0.9 1.1 70,000 Max Min 6 60 42 18 18 12 12 1 1 0.45 0.45 2 2 DDR333 MCP MEMORY Max Unit ns ns Note 1,2 70,000 ns ns ns ns ns tCK tCK 3 0.55 0.55 5.5 5.5 0.5 1.1 0.6 1.25 tCK tCK ns ns ns tCK tCK tCK ns tCK 5 4 0.6 0.6 tCK tCK tCK tCK 1.1 tCK 7 ns 8 ns 7 8 Address and Control Input hold time Address & Control input pulse width DQ & DM setup time to DQS 6,7 ns 6,8 ns 6,7 6,8 ns ns 5.5 0.6 ns tCK DQ & DM hold time to DQS DQ & DM input pulse width DQ & DQS low-impedence time from CK/CK DQ & DQS high-impedence time from CK/CK DQS write postamble time - 53 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY Parameter DQS write preamble time Refresh interval time Mode register set cycle time Power down exit time CKE min. pulse width(high and low pulse width) Auto refresh cycle time Exit self refresh to active command Data hold from DQS to earliest DQ edge Data hold skew factor Clock half period Symbol tWPRE tREF tMRD tPDEX tCKE tRFC tXSR tQH tQHS tHP DDR400 Min 0.25 64 2 2 2 120 120 tHPmin tQHS 0.5 tCLmin or tCHmin 2 1 2 120 120 Max Min 0.25 DDR333 Max 64 Unit tCK ms tCK tCK tCK ns ns ns Note 9 tHPmin tQHS 0.65 tCLmin or tCHmin ns ns NOTE : 1) tCK(max) value is measured at 100ns. 2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL(=2*tCK). tDAL =(tWR/tCK) + (tRP/tCK) 4) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25C). tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page). 5) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating Data Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/ SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. 7) Input slew rate 1.0 V/ ns. 8) Input slew rate 0.5V/ns and < 1.0V/ns. 9) Maximum burst refresh cycle : 8 - 54 - Revision 1.3 November 2009 K524G2GACB-A050 8. AC Operating Test Conditions (VDD = 1.7V to 1.95V, TC = -25C to 85C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition Value 0.8 x VDDQ / 0.2 x VDDQ 0.5 x VDDQ 1.0 0.5 x VDDQ See Figure 6 MCP MEMORY Unit V V V/ns V 1.8V 13.9K Output 10.6K 20pF - VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA - VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA Figure 5. DC Output Load Circuit Vtt=0.5 x VDDQ 50 Output Z0=50 Test load values need to be proportional to the driver strength which is set by the controller. - Test load for Full Driver Strength Buffer (20pF) - Test load for Half Driver Strength Buffer (10pF) Figure 6. AC Output Load Circuit 1), 2) NOTE : 1) The circuit shown above represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will used IBIS or other simulations tools to correlate the timing reference load to system environment. Manufacturers will correlate to their poduction test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half strength driver with a nominal 10pF load parameters tAC and tQH are expected to be in ther same range. However, these parameters are not subject to production test but are estimated by design / characterization. Use of IBIS or other simulation tolls for system design validation is suggested. 2) Based on nominal impedance at 0.5 x VDDQ. The impedence for Half(1/2) Driver Strength is designed 55ohm. And for other Driver Strength, it is designed proportionally. - 55 - Revision 1.3 November 2009 K524G2GACB-A050 9. Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25C, f=100MHz) Parameter Input capacitance (A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 1.5 1.5 2.0 2.0 MCP MEMORY Max 3.0 3.5 4.5 4.5 Unit pF pF pF pF - 56 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY 10. AC Overshoot/Undershoot Specification for Address & Control Pins Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS Specification 0.9V 0.9V 3V-ns 3V-ns Maximum Amplitude Overshoot Area Volts (V) VDD VSS Maximum Amplitude Time (ns) Undershoot Area Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins 11. AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ Specification 0.9V 0.9V 3V-ns 3V-ns Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Maximum Amplitude Time (ns) Undershoot Area Figure 8. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins - 57 - Revision 1.3 November 2009 K524G2GACB-A050 12. Command Truth Table Command Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H CKEn X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H V V BA0,1 MCP MEMORY A10/AP OP CODE X A13,A11, A9~A0 Note 1, 2 3 3 3 3 L H H X Row Address L H L H X V X L H X Column Address (A0~A9) Column Address (A0~A9) Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable 4 4 4 4, 6 7 H H H X X X L L L H L X H L H L H H L X H X X H X H X L H H X H X X H X H L L L X H X X H X H V Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Exit DM No operation (NOP) : Not defined 5 Active Power Down H L H L H L X X L H H H X X H X H X 8 9 9 X H L X H (V=Valid, X=Don't Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM. - 58 - Revision 1.3 November 2009 K524G2GACB-A050 13. Functional Truth Table Current State CS L L PRECHARGE STANDBY L L L L L L L L L L L L L L L L L L L L RAS H H L L L L H H H L L L L H H H L L L L H H CAS H L H H L L H L L H H L L H L L H H L L H L WE L X H L H L L H L H L H L L H L H L H L L H X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA MCP MEMORY Action ILLEGAL2) ILLEGAL2) Bank Active, Latch RA ILLEGAL4) AUTO-Refresh5) Mode Register Set5) NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL2) Precharge/Precharge All ILLEGAL ILLEGAL Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge3) ILLEGAL Bank Active/ILLEGAL2) Terminate Burst, Precharge10) ILLEGAL ILLEGAL ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge3) Terminate Burst, Latch CA, Begin new Write, Determine AutoPrecharge3) Bank Active/ILLEGAL2) Terminate Burst With DM=High, Precharge10) ILLEGAL ILLEGAL ILLEGAL 6) ILLEGAL 6) 6) ILLEGAL ILLEGAL ACTIVE STANDBY READ WRITE L H L L BA, CA, A10 WRITE/WRITEA L L L L L READ with AUTO PRECHARGE6) (READA) L L L L L L L L L L H H H L L L L H H L L H L L H H L L H L H L L H L H L H L BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS - 59 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY Current State CS L L L L L L L L L RAS H H H L L L L H H L L L L H H L L L L H H H L L L L H H L L L L H H L L L L CAS H L L H H L L H L H H L L H L H H L L H L L H H L L H L H H L L H L H H L L WE L H L H L H L L X H L H L L X H L H L L H L H L H L L X H L H L L X H L H L X Address BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS ILLEGAL 7) 7) 7) 7) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) ILLEGAL2) Action WRITE with AUTO RECHARGE7) (WRITEA) PRECHARGING (DURING tRP) L L L L L NOP4)(Idle after tRP) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) ILLEGAL2) ILLEGAL2) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) WRITE ILLEGAL2) ILLEGAL2) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L L L L L L L WRITE RECOVERING (DURING tWR OR tCDLR) L L L L L L L REFRESHING L L L L L L L L L L MODE REGISTER SETTING - 60 - Revision 1.3 November 2009 K524G2GACB-A050 Current State CKE n-1 L L SELFREFRESHING8) L L L L POWER DOWN L L H H H ALL BANKS IDLE9) H H H H L CKE n H H H H H L H L H L L L L L L X CS H L L L L X X X X L H L L L L X RAS X H H H L X X X X L X H H H L X CAS X H H L X X X X X L X H H L X X WE X H L X X X X X X H X H L X X X Add X X X X X X X X X X X X X X X X Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) MCP MEMORY Action Exit Power Down(Idle after tPDEX) NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State=Power Down (H=High Level, L=Low level, X=Dont Care) NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh can be entered only from All Bank Idle state. - 61 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY MOBILE DDR SDRAM Device Operations & Timing Diagram - 62 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY Device Operations - 63 - Revision 1.3 November 2009 K524G2GACB-A050 1. Precharge MCP MEMORY The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Table 1. Bank selection for precharge by Bank address bits A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks 2. No Operation(NOP) & Device Deselect The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is activated and RAS, CAS and WE are deactivated. Both Device Deselect and NOP command can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation, the operation will be completed. - 64 - Revision 1.3 November 2009 K524G2GACB-A050 3. Row Active MCP MEMORY The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The Mobile DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time, tRCD(min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay time, tRRD(min). Any system or application incorporating random access memory products should be properly designed, tested and qulifided to ensure proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or addresses may result in reduction of product life. Figure 1. Bank Activation Command Cycle timing 0 CK CK Address Bank A Row Addr. Bank A Activate Bank A Col. Addr. RAS-CAS delay(tRCD) Command NOP NOP Write A with Auto Precharge NOP NOP ROW Cycle Time(tRC) Bank B Row Addr. Bank B Activate Bank A Row. Addr. Bank A Activate 1 2 3 4 5 Tn Tn+1 Tn+2 RAS-RAS delay time(tRRD) NOP : Dont care 4. Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS cycle. 5. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS cycle. - 65 - Revision 1.3 November 2009 K524G2GACB-A050 6. Burst Read Operation MCP MEMORY Burst Read operation in Mobile DDR SDRAM is in the same manner as the Mobile SDR SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8, 16). The first output data is available with a CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by Mobile DDR SDRAM until the burst length is completed. Figure 2. Burst read operation timing 0 CK CK Command READ A NOP NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 tDQSCK DQS Hi-Z tRPRE Preamble tAC DQs Hi-Z tRPST Postamble Dout 0 Dout 1 Dout 2 Dout 3 NOTE : 1) Burst Length=4, CAS Latency= 3 - 66 - Revision 1.3 November 2009 K524G2GACB-A050 7. Burst Write Operation MCP MEMORY The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. Figure 3. Burst write operation timing 0 CK CK Command tDQSS(max) DQS Hi-Z NOP WRITEA NOP WRITEB NOP NOP NOP NOP tWR 1 2 3 4 5 6 7 8 NOP tDQSS(max) tWPREH tWPRES DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3 tDQSS(min) DQS Hi-Z tDQSS(min) tWPRES tWPREH tWR DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3 tDS tDH NOTE : 1) Burst Length=4 2) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. - 67 - Revision 1.3 November 2009 K524G2GACB-A050 8. Read Interrupted by a Read MCP MEMORY A Burst Read can be interrupted by new Read command of any bank before completion of the burst. When the previous burst is interrupted, the new address with the full burst length override the remaining address. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. Figure 4. Read interrupted by a read timing 0 CK CK Command 1 2 3 4 5 6 7 8 tCCD(min) READ READ NOP NOP NOP NOP NOP NOP NOP DQS Hi-Z tDQSCK tRPRE Preamble tRPST Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3 DQs Hi-Z NOTE : 1) Burst Length=4, CAS Latency=3 9. Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs(Output drivers) in a high impedance state. Figure 5. Read interrupted by a write and burst stop timing. 0 CK CK Command READ Burst Stop NOP NOP NOP WRITE NOP NOP NOP 1 2 3 4 5 6 7 8 tDQSCK DQS Hi-Z tRPRE tAC tDQSS tWPREH tRPST tWPRES Dout 0 Dout 1 Din 0 Din 1 Din 2 tWPST Din 3 DQs Hi-Z tWPRE NOTE : 1) Burst Length=4, CAS Latency=3 The following functionality establishes how a Write command may interrupt a burst Read. 1. For Write commands interrupting a burst Read, a Burst Terminate command is required to stop the burst read and tri-state the DQ bus prior to valid input write data. Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. - 68 - Revision 1.3 November 2009 K524G2GACB-A050 10. Read Interrupted by a Precharge MCP MEMORY A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. The latency from a precharge command to invalid output is equivalent to the CAS latency. Figure 6. Read interrupted by a precharge timing CK CK 1tCK Command READ Precharge NOP NOP NOP NOP NOP NOP NOP 0 1 2 3 4 5 6 7 8 DQS Hi-Z tDQSCK tRPRE tAC Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 DQs Hi-Z Interrupted by precharge NOTE : 1) Burst Length=8, CAS Latency=3 When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is completed. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (Row Precharge time). 2. When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst with the last valid data word presented on DQ pins at CL-1(CL=CAS Latency) clock cycles after the command has been issued. Once the last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising clock that comes CL(CL=CAS Latency) clock cycles before the end of the Read burst. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock edge).In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. - 69 - Revision 1.3 November 2009 K524G2GACB-A050 11. Write Interrupted by a Write MCP MEMORY A Burst Write can be interrupted by a new Write command before completion of the burst, where the interval between the successive Write commands must be at least one clock cycle(tCCD(min)). When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Figure 7. Write interrupted by a write timing CK CK tCCD(min) Command NOP WRITE A WRITE b NOP NOP NOP NOP NOP NOP 0 1 2 3 4 5 6 7 8 DQS Hi-Z DQs NOTE : 1) Burst Length=4 Hi-Z Din A0 Din A1 Din B0 Din B1 Din B2 Din B3 - 70 - Revision 1.3 November 2009 K524G2GACB-A050 12. Write Interrupted by a Precharge & DM MCP MEMORY A burst write operation can be interrupted by a precharge of the same bank before completion of the burst. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. Figure 8. Write interrupted by a precharge and DM timing 0 CK CK Command tDQSS(max) DQS Hi-Z NOP WRITE A NOP NOP NOP NOP tWR 1 2 3 4 5 6 7 8 PrechargeA WRITE B NOP tDQSS(max) tWPREH tDQSS(max) tWPREH tWPRES DQs Hi-Z tWPRES Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 DM tDQSS(min) DQS Hi-Z tDQSS(min) tWPRES tWPREH tWR tDQSS(min) tWPRES tWPREH DQs Hi-Z Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 Dinb2 DM NOTE : 1) Burst Length=8 Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow ''write recovery'' which is the time required by a Mobile DDR SDRAM core to properly store a full ''0'' or ''1'' level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronized with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. - 71 - Revision 1.3 November 2009 K524G2GACB-A050 13. Write Interrupted by a Read & DM MCP MEMORY A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. Figure 9. Write interrupted by a Read and DM timing 0 CK CK Command DQSS(max) DQS Hi-Z tWPRES 1 2 3 4 5 6 7 8 9 NOP WRITE NOP NOP NOP tCDLR READ NOP NOP NOP NOP NOP tDQSS(max) 5) DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 Dout2 Dout3 Dout4 DM DQSS(min) DQS Hi-Z tWPRES tDQSS(min) tCDLR 5) DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 Dout2 Dout3 Dout4 DM NOTE : 1) Burst Length=8, CAS Latency=3 The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For Read commands interrupting a burst Write, the DM pin must be used to mask the input data words whcich immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM. 5. Refer to Burst write operation. - 72 - Revision 1.3 November 2009 K524G2GACB-A050 14. Burst Stop MCP MEMORY The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. However, the burst stop command is not supported during a burst write operation. Figure 10. Burst stop timing 0 CK CK Command READ A Burst Stop NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 The burst read ends after a delay equal to the CAS latency. DQS Hi-Z DQs Hi-Z Dout 0 Dout 1 NOTE : 1) Burst Length=4, CAS Latency= 3 The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required: 1. The Burst Stop command may only be issued on the rising edge of the input clock, CK. 2. Burst Stop is only a valid command during Read bursts. 3. Burst Stop during a Write burst is undefined and shall not be used. 4. Burst Stop applies to all burst lengths. 5. Burst Stop is an undefined command during Read with autoprecharge and shall not be used. 6. When terminating a burst Read command, the BST command must be issued LBST ("BST Latency") clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). - 73 - Revision 1.3 November 2009 K524G2GACB-A050 15. DM masking MCP MEMORY The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated(DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe. Figure 11. DM masking timing 0 CK CK Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 tDQSS DQS Hi-Z tWPRES tWPREH DQs Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7 Hi-Z DM masked by DM=H NOTE : 1) Burst Length=8 - 74 - Revision 1.3 November 2009 K524G2GACB-A050 16. Read With Auto Precharge MCP MEMORY If A10/AP is high when read command is issued , the read with auto-precharge function is performed. If a read with auto-precharge command is issued, the Mobile DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. Figure 12. Read with auto precharge timing 0 CK CK Command BANK A ACTIVE NOP NOP NOP READ A Auto Precharge 1 2 3 4 5 6 7 8 9 10 11 NOP NOP NOP NOP NOP NOP NOP tRP DQS Hi-Z Bank can be reactivated at completion of tRP1) DQs Hi-Z tRAS(min) Dout0 Dout1 Dout2 Dout3 Auto-Precharge starts NOTE : 1) Burst Length=4, CAS Latency= 3 2) The row active command of the precharge bank can be issued after tRP from this point. Asserted command READ READ+AP Active Precharge NOTE : 1) AP = Auto Precharge For same Bank 5 READ +No AP1) READ + AP Illegal Legal 6 READ+No AP READ + AP Illegal Legal 7 Illegal Illegal Illegal Illegal 5 Legal Legal Legal Legal For Different Bank 6 Legal Legal Legal Legal 7 Legal Legal Legal Legal - 75 - Revision 1.3 November 2009 K524G2GACB-A050 17. Write with Auto Precharge MCP MEMORY If A10/AP is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). Figure 13. Write with auto precharge timing 0 CK CK Command BANK A ACTIVE NOP NOP NOP WRITE A Auto Precharge 1 2 3 4 5 6 7 8 9 10 11 12 13 NOP NOP NOP NOP NOP NOP NOP NOP NOP DQS Hi-Z Bank can be reactivated at completion of tRP Din 0 Din 1 Din 2 Din 3 DQs Hi-Z tWR tRP Internal precharge start 1) NOTE : 1) Burst Length=4 2) The row active command of the precharge bank can be issued after tRP from this point. Asserted command WRITE WRITE+ AP READ READ+AP Active Precharge For same Bank 5 WRITE+ No AP1) WRITE+ AP Illegal Illegal Illegal Illegal 6 WRITE+ No AP WRITE+ AP READ+ NO AP+DM2) READ + AP+DM Illegal Illegal 7 Illegal Illegal READ+ NO AP+DM READ + AP+DM Illegal Illegal 8 Illegal Illegal READ+ NO AP READ + AP Illegal Illegal 9 Illegal Illegal Illegal Illegal Illegal Illegal 10 Illegal Illegal Illegal Illegal Illegal Illegal 5 Legal Legal Illegal Illegal Legal Legal For Different Bank 6 Legal Legal Illegal Illegal Legal Legal 7 Legal Legal Illegal Illegal Legal Legal 8 Legal Legal Legal Legal Legal Legal 9 Legal Legal Legal Legal Legal Legal NOTE : 1) AP = Auto Precharge 2) DM : Refer to "27. Write Interrupted by Precharge & DM ". - 76 - Revision 1.3 November 2009 K524G2GACB-A050 18. Auto Refresh & Self Refresh 18.1. Auto Refresh MCP MEMORY An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. Once this cycle has been started, no control of the external address pins are required because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). Figure 14. Auto refresh timing CK CK Command PRE NOP NOP Auto Refresh NOP NOP NOP ACT NOP NOP CKE = High tRP tRFC(min) DQ DQS High-Z High-Z NOTE : 1) tRP=3CLK 2) Device must be in the all banks idle state prior to entering Auto refresh mode. 18.2. Self Refresh A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including system clock(CK, CK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. Before returning CKE high to exit the Self Refresh mode, apply stable clock input signal with Deselect or NOP command asserted. Figure 15. Self refresh timing CK CK Self Refresh Stable Clock NOP NOP NOP Command NOP NOP Active NOP tRFC tXSR(min) tIS DQ DQS High-Z High-Z CKE tIS NOTE : 1) Device must be in the all banks idle state prior to entering Self Refresh mode. 2) The minimum time that the device must remain in Self Refresh mode si tRFC. - 77 - Revision 1.3 November 2009 K524G2GACB-A050 19. Power down MCP MEMORY The device enters power down mode when CKE Low,and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set in high for at least tPDEX prior to Row active command. Refresh operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. Figure 16. Power down entry and exit timing CK CK Command Precharge NOP NOP Precharge power down Entry Precharge power Active down Exit (NOP) Active power down Entry Active power down Exit Read tCKE tPDEX tCKE tIS DQ tIS High-Z tIS CKE tIS DQS High-Z NOTE : 1) Device must be in the all banks idle state prior to entering Power Down mode. 2) The minimum power down duration is specified by tCKE. - 78 - Revision 1.3 November 2009 K524G2GACB-A050 20. Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption. MCP MEMORY The LPDDR SDRAM supports clock stop under the following conditions : - the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pulses per access command depends on the device's AC timing parameters and the clock requency; - the related timing conditions(tRCD, tWR, tRP, tRFC, tMRD) has been met; - CKE is held High When all conditions have been met, the device is either in "idle state"or "row active state" and clock stop mode may be entered with CK held Low and CK held Hight. Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command any be applied. Additional clock pulses might be required depending on the system characteristics. Figure 17 shows clock stop mode entry and exit. - Initially the device is in clock stop mode - The clock is restarted with the rising edge of T0 and a NOP on the command inputs - With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command is completed. - Tn is the last clock pulse required by the access command latched with T1 - The clock can be stopped after Tn. Figure 17. Clock Stop Mode Entry and Exit T0 CK T1 T2 Tn ~ ~ CK CKE ~~ Timing Condition ~ ~~ ~ ~~~~ Command Address DQ, DQS NOP CMD NOP NOP NOP Valid High-Z ~~~~ Clock Stopped Exit Valid Clock Command Stop Mode Enter clock Stop Mode = Don't Care ~ - 79 - Revision 1.3 November 2009 K524G2GACB-A050 MCP MEMORY Timing Diagram - 80 - Revision 1.3 November 2009 K524G2GACB-A050 21. Power Up Sequence for Mobile DDR SDRAM Figure 18. Power Up Sequence for Mobile DDR SDRAM CK CK MCP MEMORY CKE HiGH CS RAS CAS WE ADDR Key Key RAa BA0 BA1 A10/AP Key Key RAa DQs Hi-Z Hi-Z Hi-Z DM tRP Precharge (All Bank) Auto Refresh tRFC Auto Refresh tRFC Normal MRS Row Active (A-Bank) Extended MRS : Don't care NOTE : 1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2) Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3) Issue precharge commands for all banks of the devices. 4) Issue 2 or more auto-refresh commands. 5) Issue a mode register set command to initialize the mode register. 6) Issue a extended mode register set command for the desired operating modes after normal MRS. The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. All banks have to be in idle state prior to adjusting MRS and EMRS set. - 81 - Revision 1.3 November 2009 K524G2GACB-A050 22. Basic Timing Figure 19. Basic Timing (Setup, Hold and Access Time @BL=4, CL=3) tCH tCL tCK tCH tCL tCK MCP MEMORY 0 CK CK CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CS tIS tIH RAS CAS WE BA0, BA1 BAa BAa BAb A10/AP Ra ADDR (A0~An) Ra Ca Cb tDQSS tDSC tDQSL tWPST DQS Hi-Z tRPRE tRPST Hi-Z tWPRES tDQSH tWPREH Hi-Z tDQSCK DQs Hi-Z tAC Qa0 Qa1 Qa2 Qa3 Hi-Z Db0 Db1 Db2 Db3 Hi-Z tQHS tDS tDH DM COMMAND ACTIVE READ WRITE : Don't care - 82 - Revision 1.3 November 2009 K524G2GACB-A050 23. Multi Bank Interleaving READ Figure 20. Multi Bank Interleaving READ (@BL=4, CL=3) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb ADDR (A0~An) Ra Rb Ca Cb tRRD DQS Hi-Z tCCD DQs Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 DM tRCD COMMAND ACTIVE ACTIVE READ READ : Don't care - 83 - Revision 1.3 November 2009 K524G2GACB-A050 24. Multi Bank Interleaving WRITE Figure 21. Multi Bank Interleaving WRITE (@BL=4) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb ADDR (A0~An) Ra Rb Ca Cb tRRD DQS Hi-Z tCCD DQs Hi-Z Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM tRCD COMMAND ACTIVE ACTIVE WRITE WRITE : Don't care - 84 - Revision 1.3 November 2009 K524G2GACB-A050 25. Read with Auto Precharge Figure 22. Read with Auto Precharge (@BL=8) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP Ra ADDR (A0~An) Ca Ra Auto precharge start tRP NOTE1) DQS (CL=3) DQs (CL=3) Hi-Z Hi-Z Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 DM COMMAND READ ACTIVE : Don't care NOTE : 1) The row active command of the precharge bank can be issued after tRP from this point. - 85 - Revision 1.3 November 2009 K524G2GACB-A050 26. Write with Auto Precharge Figure 23. Write with Auto Precharge (@BL=8) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP Ra ADDR (A0~An) Ca Ra tWR DQS Auto precharge start tRP NOTE1) Hi-Z DQs Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Hi-Z DM COMMAND WRITE ACTIVE : Don't care NOTE : 1) The row active command of the precharge bank can be issued after tRP from this point - 86 - Revision 1.3 November 2009 K524G2GACB-A050 27. Write followed by Precharge Figure 24. Write followed by Precharge (@BL=4) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ca tWR DQS Hi-Z DQs Da0 Da1 Da2 Da3 Hi-Z DM COMMAND WRITE PRE CHARGE : Don't care - 87 - Revision 1.3 November 2009 K524G2GACB-A050 28. Write Interrupted by Precharge & DM Figure 25. Write Interrupted by Precharge & DM (@BL=8) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa BAb BAc A10/AP ADDR (A0~An) Ca Cb Cc DQS Hi-Z DQs Hi-Z Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dc4 Dc5 Dc6 Dc7 DM tWR COMMAND WRITE PRE CHARGE tCCD WRITE WRITE : Don't care - 88 - Revision 1.3 November 2009 K524G2GACB-A050 29. Write Interrupted by a Read Figure 26. Write Interrupted by a Read (@BL=8, CL=3) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) DQS Hi-Z Ca Cb DQs Hi-Z Da0 Da1 Da2 Da3 Da4 Da5 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Masked by DM DM tCDLR COMMAND WRITE READ : Don't care - 89 - Revision 1.3 November 2009 K524G2GACB-A050 30. Read Interrupted by Precharge Figure 27. Read Interrupted by Precharge (@BL=8, CL=3) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ca DQS Hi-Z 2 tCK Valid DQs Hi-Z Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DM COMMAND READ PRE CHARGE : Don't care - 90 - Revision 1.3 November 2009 K524G2GACB-A050 31. Read Interrupted by a Write & Burst Stop Figure 28. Read Interrupted by a Write & Burst Stop (@BL=8, CL=3) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) Ca Cb DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM COMMAND READ Burst Stop WRITE : Don't care - 91 - Revision 1.3 November 2009 K524G2GACB-A050 32. Read Interrupted by a Read Figure 29. Read Interrupted by a Read (@BL=8, CL=3) 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) Ca Cb DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM COMMAND READ READ : Don't care - 92 - Revision 1.3 November 2009 K524G2GACB-A050 33. DM Function Figure 30. DM Function (@BL=8) only for write 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa A10/AP ADDR (A0~An) Ca DQS Hi-Z DQs Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Hi-Z DM COMMAND WRITE : Don't care - 93 - Revision 1.3 November 2009 K524G2GACB-A050 34. Mode Register Set Figure 31. Mode Register Set 0 CK CK MCP MEMORY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CKE HIGH CS RAS CAS WE BA0,BA1 Key A10/AP Key ADDRESS KEY ADDR (A0~An) DQS Key Hi-Z Hi-Z tRP tMRD DQs DM COMMAND Precharge Command All Bank MRS Command Any Command : Don't care - 94 - Revision 1.3 November 2009 |
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